Volume 2, Number 1 (2019)
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Home > Journals > SCIREA Journal of Electrics, Communication > Archive > Paper Information

Realization of a Low Power and Area-Efficient VLSI Architecture for Carry Select Adder using Multiplexer Based Adders

Volume 2, Issue 1, February 2019    |    PP. 19-38    |PDF (775 K)|    Pub. Date: May 5, 2019
   310 Downloads     2780 Views  

Bala Sindhuri Kandula, Department of Electronics and communication Engineering, University College of Engineering,JNTUK,Kakinada, India
K.Padma Vasavi, SVECW, Bhimavram, India
I.Santi Prabha, Department of Electronics and communication Engineering, University College of Engineering,JNTUK,Kakinada, India

Carry Select Adder (CSLA) is the most popular choice for multiply and accumulate operations because of its high performance in fast computations. However, the major drawback for CSLA is resource utilization as it occupies more area and power when compared to Ripple Carry Adder (RCA). Low Power and area efficiency can be achieved by using multiplexer based adders as the switching activity reduces the resource utilization. The proposed architecture is designed by using two bit adders using 4:1 multiplexers and synthesized in cadence RTL compiler using 90nm technology. The performance evaluation of the proposed architecture in terms of area and power is compared with Square Root Carry Select Adder (SQRT CSLA), Square Root Carry Select Adder using Kogge-stone Adder (SQRT-KSA), Square Root Carry Select Adder using Binary to Excess-1 Converter (SQRTCSLA-BEC),Kogge-stone Square Root Carry Select Adder using Binary to Excess-1 Converter (SQRTKSA-BEC)architectures for different bit depths ranging from 16 bits to 64 bits. The Proposed architecture is proved to be efficient both in terms of area and power when compared to SQRTCSLA, SQRT-KSA, SQRTCSLA-BEC, SQRTKSA-BEC architectures

Carry Select Adder (CSLA), Multiplexer Based Adder,Area and Power Efficient, Two Bit Adder.

Cite this paper
Bala Sindhuri Kandula, K.Padma Vasavi, I.Santi Prabha, Realization of a Low Power and Area-Efficient VLSI Architecture for Carry Select Adder using Multiplexer Based Adders, SCIREA Journal of Electrics, Communication. Vol. 2 , No. 1 , 2019 , pp. 19 - 38 .


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