Home > Journals > SCIREA Journal of Electrical Engineering > Archive > Paper Information

A Performance Comparison Between Different Approaches for Implementation of FPGA-based Arbiter Physical Unclonable Function 

Volume 7, Issue 1, February 2022    |    PP. 1-21    |PDF (907 K)|    Pub. Date: January 20, 2022
DOI: 10.54647/dee47263    12 Downloads     447 Views  

Author(s)
Swati K. Kulkarni, Applied Electronics Department, Gulbarga University, Gulbarga-585106, India
Vani R. M, University Science Instrumentation Center, Gulbarga University, Gulbarga-585106, India
P. V. Hunagund, University Science Instrumentation Center, Gulbarga University, Gulbarga-585106, India

Abstract
In our daily lives, embedded and Internet of Things (IoT) applications are becoming extremely important. It advised using intellectual property (IP) while developing embedded and IoT applications. Hardware security and electronic component counterfeiting pose a threat to IoT devices and IPs. Another consideration is that today's electronic industry must contend with a slew of security concerns, including IC cloning, reverse engineering, overbuilding, and physical manipulation. PUF is a part of hardware security, utilized for device authentication, IP core protection, and the creation of cryptographic keys. The PUF uses intrinsic properties of IC fabrication variances to deliver an exclusive identifier for every device. PUF inherently provides security properties. Already, many researchers have concluded that arbiter and SRAM PUF architectures are unsuitable for FPGAs because their delay skew is higher than the random manufacturing process variations. The designer should have an accurate understanding of the FPGA platform. We used the Xilinx FPGA to develop and compare three versions of Arbiters PUF: 64-bit Classical Arbiter PUF, 64-bit,128-bit PDL-based Arbiter PUF, and Wide multiplexer-based Arbiter PUF. A comparison was performed based on the design approach, resource consumption, power analysis, and PUF feature.

Keywords
Arbiter PUF, Programable Delay Line, Register Transfer Level (RTL), FPGA-SOC, Simulation, Synthesis, Placement & Routing and Hardware Validation etc.

Cite this paper
Swati K. Kulkarni, Vani R. M, P. V. Hunagund, A Performance Comparison Between Different Approaches for Implementation of FPGA-based Arbiter Physical Unclonable Function , SCIREA Journal of Electrical Engineering. Vol. 7 , No. 1 , 2022 , pp. 1 - 21 . https://doi.org/10.54647/dee47263

References

[ 1 ] Pappu R, Recht B, Taylor J, Gershenfeld N. Physical one-way functions. Science. 2002 Sep 20;297(5589):2026-30.
[ 2 ] Gassend B, Clarke D, Van Dijk M, Devadas S. Silicon physical random functions. InProceedings of the 9th ACM Conference on Computer and Communications Security 2002 Nov 18 (pp. 148-160).
[ 3 ] Suh GE, Devadas S. Physical unclonable functions for device authentication and secret key generation. In2007 44th ACM/IEEE Design Automation Conference 2007 Jun 4 (pp. 9-14). IEEE.
[ 4 ] Suh GE, Devadas S. Physical unclonable functions for device authentication and secret key generation. In2007 44th ACM/IEEE Design Automation Conference 2007 Jun 4 (pp. 9-14). IEEE.
[ 5 ] Maiti A, Schaumont P. Improved ring oscillator PUF: An FPGA-friendly secure primitive. Journal of cryptology. 2011 Apr;24(2):375-97.
[ 6 ] Rührmair U, Holcomb DE. PUFs at a glance. In2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) 2014 Mar 24 (pp. 1-6). IEEE.
[ 7 ] Lee JW, Lim D, Gassend B, Suh GE, Van Dijk M, Devadas S. A technique to build a secret key in integrated circuits for identification and authentication applications. In2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No. 04CH37525) 2004 Jun 17 (pp. 176-179). IEEE.
[ 8 ] Kumar SS, Guajardo J, Maes R, Schrijen GJ, Tuyls P. The butterfly PUF protecting IP on every FPGA. In2008 IEEE International Workshop on Hardware-Oriented Security and Trust 2008 Jun 9 (pp. 67-70). IEEE.
[ 9 ] Suzuki D, Shimizu K. The glitch PUF: A new delay-PUF architecture exploiting glitch shapes. InInternational Workshop on Cryptographic Hardware and Embedded Systems 2010 Aug 17 (pp. 366-382). Springer, Berlin, Heidelberg.
[ 10 ] Holcomb DE, Burleson WP, Fu K. Initial SRAM state as a fingerprint and source of true random numbers for RFID tags. InProceedings of the Conference on RFID Security 2007 Jul 11 (Vol. 7, No. 2, p. 01).
[ 11 ] Hata H, Ichikawa S. FPGA implementation of metastability-based true random number generator. IEICE TRANSACTIONS on Information and Systems. 2012 Feb 1;95(2):426-36.Handschuh H, Schrijen GJ, Tuyls P. Hardware intrinsic security from physically unclonable functions. InTowards Hardware-Intrinsic Security 2010 (pp. 39-53). Springer, Berlin, Heidelberg.
[ 12 ] Sklavos N. Securing communication devices via physical unclonable functions (PUFs). InISSE 2013 Securing Electronic Business Processes 2013 (pp. 253-261). Springer Vieweg, Wiesbaden.
[ 13 ] Rührmair U, Busch H, Katzenbeisser S. Strong PUFs: models, constructions, and security proofs. InTowards hardware-intrinsic security 2010 (pp. 79-96). Springer, Berlin, Heidelberg.
[ 14 ] Zhang JL, Wu Q, Ding YP, Lv YQ, Zhou Q, Xia ZH, Sun XM, Wang XW. Techniques for design and implementation of an FPGA-specific physical unclonable function. Journal of Computer Science and Technology. 2016 Jan 1;31(1):124-36.
[ 15 ] Morozov S, Maiti A, Schaumont P. A Comparative Analysis of Delay Based PUF Implementations on FPGA. IACR Cryptol. ePrint Arch.. 2009 Dec 19;2009:629.
[ 16 ] Guajardo J, Kumar SS, Schrijen GJ, Tuyls P. FPGA intrinsic PUFs and their use for IP protection. InInternational workshop on cryptographic hardware and embedded systems 2007 Sep 10 (pp. 63-80). Springer, Berlin, Heidelberg.
[ 17 ] Vaikuntapu R, Bhargava L, Sahula V. Golden IC free methodology for hardware trojan detection using symmetric path delays. In2016 20th International Symposium on VLSI Design and Test (VDAT) 2016 May 24 (pp. 1-2). IEEE.
[ 18 ] Ning H, Farha F, Ullah A, Mao L. Physical unclonable function: architectures, applications and challenges for dependable security. IET Circuits, Devices & Systems. 2020 Feb 7;14(4):407-24.
[ 19 ] Sahoo DP, Nguyen PH, Chakraborty RS, Mukhopadhyay D. Architectural Bias: a Novel Statistical Metric to Evaluate Arbiter PUF Variants. IACR Cryptol. ePrint Arch.. 2016;2016:57.
[ 20 ] Dubrova E. A reconfigurable arbiter PUF with 4 x 4 switch blocks. In2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) 2018 May 16 (pp. 31-37). IEEE.
[ 21 ] Chatterjee D, Mukhopadhyay D, Hazra A. Interpose PUF can be PAC Learned. IACR Cryptol. ePrint Arch.. 2020;2020:471.
[ 22 ] Hori Y, Yoshida T, Katashita T, Satoh A. Quantitative and statistical performance evaluation of arbiter physical unclonable functions on FPGAs. In2010 International Conference on Reconfigurable Computing and FPGAs 2010 Dec 13 (pp. 298-303). IEEE.
[ 23 ] Chatterjee U, Chakraborty RS, Kapoor H, Mukhopadhyay D. Theory and application of delay constraints in arbiter PUF. ACM Transactions on Embedded Computing Systems (TECS). 2016 Jan 28;15(1):1-20.
[ 24 ] Alkatheiri MS, Zhuang Y, Korobkov M, Sangi AR. An experimental study of the state-of-the-art PUFs implemented on FPGAs. In2017 IEEE Conference on Dependable and Secure Computing 2017 Aug 7 (pp. 174-180). IEEE.
[ 25 ] Devadas S, Kharaya A, Koushanfar F, Majzoobi M. Automated design, implementation, and evaluation of arbiter-based PUF on FPGA using programmable delay lines. 2014 Aug 18.
[ 26 ] Anandakumar NN, Hashmi MS, Sanadhya SK. Compact implementations of FPGA-based PUFs with enhanced performance. In2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) 2017 Jan 7 (pp. 161-166). IEEE.
[ 27 ] Habib B, Gaj K, Kaps JP. FPGA PUF based on programmable LUT delays. In2013 Euromicro Conference on Digital System Design 2013 Sep 4 (pp. 697-704). IEEE.
[ 28 ] Majzoobi M, Koushanfar F, Devadas S. FPGA PUF using programmable delay lines. In2010 IEEE international workshop on information forensics and security 2010 Dec 12 (pp. 1-6). IEEE.
[ 29 ] Tajik S, Dietz E, Frohmann S, Seifert JP, Nedospasov D, Helfmeier C, Boit C, Dittrich H. Physical characterization of arbiter PUFs. InInternational Workshop on Cryptographic Hardware and Embedded Systems 2014 Sep 23 (pp. 493-509). Springer, Berlin, Heidelberg.
[ 30 ] Sahoo DP, Chakraborty RS, Mukhopadhyay D. Towards ideal arbiter PUF design on Xilinx FPGA: A practitioner's perspective. In2015 Euromicro Conference on Digital System Design 2015 Aug 26 (pp. 559-562). IEEE.
[ 31 ] Gehrer S, Sigl G. Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation. In2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) 2015 Jun 29 (pp. 1-6). IEEE.
[ 32 ] Pei S, Zhang J, Wang R. A low-overhead RO PUF design for Xilinx FPGAs. IEICE Electronics Express. 2018;15(5):20180093-.
[ 33 ] Machida T, Yamamoto D, Iwamoto M, Sakiyama K. A new arbiter PUF for enhancing unpredictability on FPGA. The Scientific World Journal. 2015 Jan 1;2015.
[ 34 ] Machida T, Yamamoto D, Iwamoto M, Sakiyama K. A new mode of operation for arbiter PUF to improve uniqueness on FPGA. In2014 Federated Conference on Computer Science and Information Systems 2014 Sep 7 (pp. 871-878). IEEE.
[ 35 ] Kulkarni S, Vani RM, Hunagund PV. FPGA based Hardware Security for Edge Devices in Internet of Things. In2020 5th International Conference on Communication and Electronics Systems (ICCES) 2020 Jun 10 (pp. 1133-1138). IEEE.Cui Y, Wang C, Chen Y, Wei Z, Chen M, Liu W. Dynamic Reconfigurable PUFs Based on FPGA. In2019 IEEE International Workshop on Signal Processing Systems (SiPS) 2019 Oct 20 (pp. 79-84). IEEE.
[ 36 ] Ikezaki Y, Nozaki Y, Yoshikawa M. IoT device oriented security module using PUF. In2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK) 2016 Jun 23 (pp. 1-2). IEEE.
[ 37 ] Lao Y, Parhi KK. Statistical analysis of MUX-based physical unclonable functions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2014 Apr 17;33(5):649-62.
[ 38 ] Kulkarni S, Vani RM, Hunagund PV. Designing of Arbiter PUF for Securing IP and IoT Devices. InData Intelligence and Cognitive Informatics 2021 (pp. 131-138). Springer, Singapore..
[ 39 ] Xilinx Vivado Design Suite User Guide Synthesis UG901 (v2019.2) January 27, 2020.
[ 40 ] https://www.xilinx.com/html_docs/xilinx2015_1/SDK_Doc/index.html

Submit A Manuscript
Review Manuscripts
Join As An Editorial Member
Most Views
Article
by Sergey M. Afonin
3057 Downloads 58865 Views
Article
by Jian-Qiang Wang, Chen-Xi Wang, Jian-Guo Wang, HRSCNP Research Team
15 Downloads 34541 Views
Article
by Syed Adil Hussain, Taha Hasan Associate Professor
2418 Downloads 23905 Views
Article
by Omprakash Sikhwal, Yashwant Vyas
2486 Downloads 20064 Views
Article
by Munmun Nath, Bijan Nath, Santanu Roy
2364 Downloads 19819 Views
Upcoming Conferences